1. Field of the Invention
The present invention relates to a memory.
2. Description of the Background Art
A ferroelectric memory comprising memory cells including ferroelectric capacitors is generally known as one of nonvolatile memories. Such ferroelectric memories include a one-transistor one-capacitor ferroelectric memory comprising memory cells each formed by one transistor and one ferroelectric capacitor, a one-transistor ferroelectric memory comprising memory cells each formed by one transistor having a ferroelectric capacitor and a simple matrix ferroelectric memory comprising memory cells each formed by only a ferroelectric capacitor arranged between a word line and a bit line. Each of the one-transistor ferroelectric memory and the simple matrix ferroelectric memory is constituted of a smaller number of elements as compared with the one-transistor one-capacitor ferroelectric memory, whereby the area per memory cell is reduced. Therefore, the chip area of the overall memory cell array can be reduced.
The one-transistor one-capacitor ferroelectric memory controls connection between bit lines and the ferroelectric capacitors through the transistors. Therefore, the parasitic capacitance of each bit line is decided by the sum of the wiring capacitance thereof and the diffusion capacitance (junction capacitance) of the corresponding transistor. In the simple matrix ferroelectric memory, on the other hand, each ferroelectric capacitor is directly connected to the corresponding bit line, whereby the parasitic capacitance of the bit line is the sum of the wiring capacitance thereof and the capacitance of the ferroelectric capacitor. The dielectric constant of the ferroelectric capacitor is so high that the capacitance of the ferroelectric capacitor is greater than the diffusion capacitance (junction capacitance) of a transistor with respect to the same area. Therefore, the bit line parasitic capacitance in the simple matrix ferroelectric memory is greater than that in the one-transistor one-capacitor ferroelectric memory. Further, a read voltage output to the bit line in a read operation depends on the ratio (Cs/Cb) between a cell capacitance Cs and a bit line parasitic capacitance Cb. Therefore, the read voltage can be increased as the ratio Cs/Cb is increased. In other words, the read voltage can be more increased as the bit line parasitic capacitance Cb is reduced. However, the bit line parasitic capacitance in the simple matrix ferroelectric memory is greater than that in the one-transistor one-capacitor ferroelectric memory as hereinabove described, and hence the read voltage is disadvantageously reduced in the simple matrix ferroelectric memory.
Therefore, generally proposed is a bit line hierarchical structure of bit lines divided into a main bit line and sub bit lines. A ferroelectric nonvolatile semiconductor memory having such a bit line hierarchical structure comprises bit lines divided into a main bit line and sub bit lines, a read transistor controlling the potential of the main bit line on the basis of the potential of a selected sub bit line in a read operation and a detection transistor.
In this conventional ferroelectric nonvolatile semiconductor memory, the sub bit lines are connected to the gate of the detection transistor. The main bit line is connected to a first source/drain region of the detection transistor through the read transistor. A second source/drain region of the detection transistor is connected to a power supply potential (Vcc). The conventional ferroelectric nonvolatile semiconductor memory controls ON- and OFF-states of the detection transistor through a potential corresponding to data appearing on the selected sub bit line in the read operation and applies the power supply potential (Vcc) to the main bit line through two transistors, i.e. the detection transistor and the read transistor only when the detection transistor is in an ON-state, thereby controlling the potential output to the main bit line in response to the data.
In this conventional ferroelectric nonvolatile semiconductor memory, a capacitance contributing to a bit line parasitic capacitance is limited to the capacitance of memory cells connected to the divided sub bit lines. Thus, the value of a parasitic capacitance Cb of the overall bit lines is so reduced that a read voltage can be increased.
However, the conventional ferroelectric nonvolatile semiconductor memory must be provided with the two transistors, i.e. the read transistor and the detection transistor in order to control the potential of the main bit line on the basis of the potential of the selected sub bit line in the read operation, and hence the chip area of the memory is disadvantageously increased.